Digital ASIC/EIC Design Engineer

About the role

We are partnering with an innovative semiconductor and hardware technology company that designs advanced integrated circuits. The Digital ASIC/EIC Design Engineer will join a growing engineering team to develop cutting‑edge chips for a variety of industries.

Key responsibilities

• Design and develop digital circuits for ASIC/SoC platforms.
• Define and implement RTL architecture and micro‑architecture using Verilog, SystemVerilog, or VHDL.
• Deliver block‑level and top‑level designs, including datapath, control logic, interfaces, and peripherals.
• Perform RTL simulations, validation, and gate‑level synthesis.
• Conduct static timing analysis, constraint definition, lint analysis, and logic equivalence checking.
• Support low‑power design and optimisation strategies.
• Collaborate closely with verification and physical design teams across ASIC programs.

Required profile

• Experience in digital IC, ASIC, or SoC design.
• Proficiency in RTL design (Verilog, SystemVerilog, VHDL) and ASIC design flow.
• Hands‑on experience with synthesis, timing analysis, and constraint management.
• Strong debugging and verification skills.
• Familiarity with major EDA toolchains (Cadence, Synopsys, Mentor Graphics).

Required skills

• Verilog
• SystemVerilog
• VHDL
• Python
• TCL
• Perl
• Cadence
• Synopsys
• Mentor Graphics
• Git
• Linux

What we offer

• Work on advanced semiconductor technologies.
• Join a highly skilled, collaborative engineering team.
• Clear growth opportunities within complex ASIC development programmes.
• Competitive salary range €40,000 – €50,000 (flexible for exceptional candidates).