Analog IC Design Engineer - Core Analog Blocks (Junior / Mid-level)

About the role

We are looking for an analog IC designer to focus on the core building blocks every chip depends on, such as LDOs, bandgap references, comparators, bias networks and amplifiers. You will own these blocks end‑to‑end – from specification through schematic, simulation, layout supervision and silicon bring‑up – working alongside senior designers.

Key responsibilities

• Design LDOs (with and without external capacitor), bandgap and current references, comparators, op‑amps, OTAs, bias networks and power‑management blocks from specification to tape‑out.
• Simulate across PVT corners and Monte Carlo runs, checking stability, PSRR, noise, offset, line and load transients, and start‑up behavior.
• Drive layout with attention to matching, symmetry and parasitic‑aware floorplanning; close the post‑layout loop.
• Integrate blocks at top level, handling power domains, ESD and verification together with digital and RF teams.
• Document work, participate in design reviews and support silicon evaluation and correlation with simulation.

Required profile

• MSc (or equivalent) in Electrical Engineering, Microelectronics or a related field.
• 1–5 years of hands‑on analog IC design experience (including thesis work or internships).
• Strong transistor‑level fundamentals: feedback, stability, noise, mismatch, offset and PVT variation.
• Experience with a full‑custom analog design flow – schematic capture, SPICE‑class simulation and layout – using Cadence, Synopsys or equivalent tools.
• Proactive, detail‑oriented and committed to high reliability and performance.
• Collaborative team player with good written and spoken English.
• Based in, or willing to relocate to, the Porto area.

Required skills

• Cadence (Virtuoso, Spectre) and Synopsys (Custom Compiler, PrimeSim/HSPICE) environments.
• SPICE‑class circuit simulation.
• Linux command‑line environment.
• Scripting for automation (Python, SKILL, TCL).

What we offer

• Hybrid work model: 2‑3 days per week in the Porto office, the rest remote.
• Design responsibility from day one with mentoring from senior engineers.
• Small team where your work goes directly to silicon, without layers between you and tape‑out.
• Opportunities to engage in exciting national and international projects.
• Health insurance.