Security Digital Design Engineer

About the role

Synopsys is seeking a Security Digital Design Engineer to develop secure RTL IP cores. You will work on translating security requirements into high‑performance, synthesizable hardware while ensuring thorough verification.

Key responsibilities

• Design and implement RTL in Verilog/SystemVerilog for security IP cores.
• Build and maintain UVM‑based test environments covering corner cases and attack scenarios.
• Verify IP using UVM testbenches and formal verification tools.
• Collaborate with hardware and software security engineers to evaluate functional correctness across threat models.
• Contribute to design specifications, verification plans, and documentation for global development.

Required profile

• Strong RTL design experience for hardware IP, with hands‑on Verilog/SystemVerilog coding.
• Experience in ASIC verification using SystemVerilog, UVM, or similar frameworks.
• Ability to create detailed test environment specifications mapping requirements to verification objectives.
• MSc or PhD in Electrical Engineering, Computer Science, or related field.
• Solid understanding of IC design flows, synthesis, timing analysis, and design‑for‑test concepts.

Required skills

• Verilog
• SystemVerilog
• UVM
• Formal verification
• ASIC verification
• Synthesis and timing analysis
• Design‑for‑test methodologies
• Hardware security concepts (cryptographic IP a plus)